1. Field of the Invention
The present invention generally relates to a cache memory apparatus, and a data processing apparatus containing a control processing unit using this cache memory apparatus. More specifically, the present invention is directed to a data processing apparatus containing a cache memory apparatus for storing system control information.
2. Description of the Related Art
A conventional data processing apparatus such as a microprocessor employs architecture having a single cache memory which stores thereinto both instruction information and data information. Since the conventional data processing apparatus employs such a single cache memory, the storage content of this cache memory is frequently updated due to an instruction access sequence of an application program executed by this conventional data processing apparatus and also due to a capacity of data processed by this data processing apparatus. As a result, a cache hit rate of this single cache memory is low, and a frequency degree where this data processing apparatus accesses an external storage apparatus operated in slow speeds is increased, so that performance of the entire system would be lowered.
Very recently, on the other hand, most of data processing apparatus such as microprocessors own both cache memories for storing instructions and cache memories for storing data in a separate form in order to improve cache hit rates thereof. Also, with cache memories formed in a hierarchical manner, cache hit rates may be increased in certain data processing apparatus.
The related technical ideas have been described in, for example, JP-A-6-242951, JP-A-8-16390, and U.S. Pat. No. 5,375,216. In this related art, a single cache memory apparatus is subdivided into two cache memories which are employed so as to store instructions and data respectively.
Also, as described in JP-A-5-324317, the memory sequential look-ahead apparatus is provided so as to operate the cache memory apparatus in high speeds. Further, as described in JP-A-6-110681, the information transfer paths are separately provided for the instruction-storing cache memory apparatus and the data-storing cache memory apparatus.
In addition, the publication entitled xe2x80x9cCONSTRUCTION/DESIGN OF COMPUTER, INTERFACE BETWEEN HARDWARE AND SOFTWARExe2x80x9d written by Patterson and Henecy (ISBN 4-8222-8057-8), pages 498 to 576, describes several mapping systems capable of achieving highspeed cache retrieving operations.
Also, although JP-A-3-223931 is not directed to a cache memory apparatus, this patent application describes that in the CPU system, the normal instructions and the sequential instructions are separately executed. Also, JP-A-62-231340 discloses the pipeline mounting method featured by that the process operations are subdivided every address of instruction data which is pre-loaded.
To increase the hit rates of the cache memories, the above-described conventional cache memory apparatus is subdivided into two cache memories for storing the instructions and the data. However, since this conventional cache memory apparatus does not consider the instruction access sequence of the application program but also the change in the cache memory contents caused by the capacity of the data operated by this application program, the cache hit rate for the instruction group which manages the execution of this application program and also the cache hit rate for the data group would be lowered. As a result, performance of the entire system would be deteriorated.
As one example of both the instruction group and the data group, which may manage the execution of the above-explained application program, there is provided system control information which may give adverse influences such system performance. As one example of this system control information, there are both an instruction group and a data group, which are related to an operating system constituting a base of this application program.
In JP-A-5-324317, both the instruction group and the data group used in this operating system, for example, TCB (task control block) are handled similar to both the instruction group and the data group used in the application program. As a result, when the content of the cache memory is changed due to the execution condition of this application program, both the instruction group and the data group of the operating system are adversely influenced. In the worst case, these instruction group and data group of the operating system are deleted from the cache memory, the cache hit rate is varied. Therefore, it is practically difficult to predict the behavior of the entire system.
As a consequence, in an assembled control system which requires strict timing controls, while a real-time operating system is employed as the above-explained operating system, there are many possibilities that both the instruction group and the data group of this real-time operating system are utilized outside a cache memory. Since the real-time operating system is utilized outside the cache memory, the external memory must be accessed. Since the access speed of this external memory is very slower than that of the cache memory, performance of the entire system would be deteriorated.
A first object of the present invention is to provide such a memory apparatus capable of increasing performance of an entire system, while system control data is cached without being adversely influenced by behavior of an application program.
A second object of the present invention is to realize a high-speed access operation to system control information and also to improve a cache hit rate in a cache memory apparatus.
Also, a third object of the present invention is to improve an access characteristic of a cache control operation in a central processing apparatus having an instruction group to operate a system control information group.
The above-explained first object of the present invention may be achieved by that in a cache memory apparatus for storing thereinto either a portion or all of information stored in a memory, the cache memory apparatus is comprised of: a cache memory for storing thereinto at least one of information about an instruction group related to a system control and information about a data group; an address management table for managing both an address and a range with respect to the cache memory into which the information is stored; and a selection circuit for selecting the cache memory in response to an access to the address management table. In other words, in order to achieve the above-explained first object, the present invention is featured by employing a cache memory apparatus for storing thereinto both information of an instruction group and information of a data group, which are related to a system control. Also, in order to select this cache memory apparatus, an address management table is provided so as to manage an address and a range on a memory where the above-explained information is stored. Then, the selection circuit for selecting the cache memory apparatus based on this address management table is employed. As a result, the registration of the above-explained system control information into the cache memory apparatus is no longer required. There is such an effect that the highspeed access operation to this system control information can be realized, and also the cache hit rate can be improved.
The second object of the present invention may be achieved by employing an offset management table and an instruction control apparatus in the above-explained cache memory apparatus. The offset management table manages an offset value in which an item for constituting the system control information is stored. The instruction control apparatus decodes an instruction used to operate this offset value. In other words, in order to achieve the second object, the present invention may be accomplished by employing an offset management table and an instruction control apparatus so as to effectively access the information of the instruction group and the information of the data group related to the system control. The offset management table manages an offset value which constitutes a storage position with respect to each of items which constitute the above-explained information of both the instruction group and the data group. The instruction control apparatus decodes an instruction used to operate this offset value. As a consequence, the high-speed access operation to the system control information can be realized, and also the cache hit rate can be increased in the cache memory apparatus.
The third object of the present invention may be achieved by that in a central processing apparatus equipped with the above-explained cache memory apparatus, this central processing apparatus is comprised of means for designating an entry of the offset management table so as to interpret information which is located at an offset value of the entry, and for outputting an execution address, and then the execution address is set to a program counter. As a result, the access characteristic of the cache control performed in the central processing apparatus can be improved.